1. Field of the Invention
The present invention generally relates to a clock signal generating circuit and, more particularly, to a clock signal generating circuit which generates a clock signal having a desired frequency by dividing a reference clock signal.
Recently, digital signal technology is widely used in the communication field to transmit information by a digital signal. Since there are various signal speeds for transmitting digital signals, various clock signals having different frequencies are needed. Especially, in the communication field, importance of a change of the signal speed and clock change is increased. Thus, the need for clock signals having various frequencies is increasing.
2. Description of the Related Art FIG. 1 is a block diagram of a conventional clock signal generating circuit. In the clock signal generator shown in FIG. 1, a reference clock signal is generated by a reference clock signal oscillator 31.
The reference clock signal is supplied to a counter 32. A frequency of the reference clock signal is divided in the counter 32 so as to convert the reference clock signal into a clock signal having a desired frequency. In the conventional clock signal generating circuit, only a clock signal having a multiple of the frequency of the reference clock signal can be generated.
In order to generate a clock signal having a frequency other than a multiple of the frequency of the reference clock signal, a clock signal generating circuit using a phase locked loop (PLL) circuit is used. FIG. 2 is a block diagram of a clock signal generating circuit using the PLL circuit. In FIG. 2, the reference clock signal generated by the reference clock signal oscillator 31 is supplied to a frequency divider 33. The frequency of the reference clock signal is divided by a predetermined dividing ratio by the frequency divider 33. A phase comparator 34 outputs a phase difference signal by comparing the clock signal output from the frequency divider 33 with a clock signal output from the clock signal generating circuit. The phase difference signal is filtered by a low-pass filter (LPF) 35, and the filtered phase difference signal is supplied to a voltage controlled oscillator (VCO) 36. The voltage controlled oscillator 36 varies a control voltage in accordance with the phase differential signal supplied by the low-pass filter 35. A frequency of a clock signal oscillated by the voltage controlled oscillator 36 is varied responsive to the control signal.
In the clock signal generating circuit shown in FIG. 2, the dividing ratio of the frequency divider 37 is set to a predetermined value in relation to the dividing ratio of the frequency divider 33 so that the same frequency is obtained by the frequency dividers 33 and 37. That is, the frequency of the clock signal output from the frequency divider 37 is controlled to be equal to the frequency of the clock signal output from the frequency divider 33.
The clock signal generating circuit shown in FIG. 2 can generate a clock signal having a frequency other than the frequency divided by a natural number due to the PLL circuit. However, a multiplication order of the PLL circuit may be increased due to values of the dividing ratios of the frequency dividers 33 and 37. Thus, there is a problem in that a phase noise characteristic is deteriorated or a pull-in time of a synchronization of the PLL circuit is increased.